Improved Scan Chain Stitching for Reducing Test Power
Sai Sandeep Annamareddy, Navya Mohan · 2024
In system-on-chip manufacturing tests, most often used method for attaining high test coverage is scan-based testing. Therefore, scan architecture is typically used by design for testability (DFT) designers to create tests. Nevertheless, during scan testing, the larger circuit sizes result in higher power consumption. During scan testing, high power consumption might lead to heat problems and circuit damage. Low-power scan architectures are being developed to address this. These architectures minimize total power draw during testing without sacrificing the comprehensiveness of the scan test by utilizing methods including modified scan cell design, shift power optimization, and scan chain partitioning. This makes it possible to produce chips with a reduced risk of damage and controllable heat management. This work aims at implementing an improved scan chain stitching to reduce the power consumption while testing the circuit. By determining the scan influence value and applying it to alter the flip-flop order in the scan architecture, a technique known as “scan chain stitching” can lower the test power consumption. Test data compaction, or automatic test pattern generation (ATPG) based technology, is used to further minimize the test power. The efficiency of proposed method can be evaluated by implementing on benchmark circuits from ISCAS'89. The experimental results are obtained from the Synopsys Tmax tool.