Fully Automatic Compiler Retargeting and CV-X-IF Hardware Interface Generation for RISC-V Custom Instructions
Kari Hepola, Tharaka Ranasinghe Arachchige, Joonas Multanen, Pekka Jääskeläinen · 2024
Application-specific instruction-set processors (ASIPs) can yield significantly better performance and energy efficiency results compared to general-purpose processors, while maintaining programmability. Instruction set customization raises the issue of how to integrate co-processors implementing custom instructions with the datapath, as using microarchitecture-specific interfaces lead to difficulties reusing them for other processors. Equally important is applying automatically retargeting compilation for the custom instructions to ensure easy utilization. To this end, we introduce a method for constructing an automatically retargeting compiler toolchain and a flow for generating Core-V eXtension interface compatible co-processors that can adapt to the same architecture description. We demonstrate the toolset by designing an ASIP based on the CVA6 processor for three BEEBS benchmark suite applications, which reduces the execution time $26 \%$ on average with an area overhead of $1 \%$ without affecting the clock frequency of the synthesized hardware implementation.