An FPGA-Based QC-LDPC Decoder Design
Nan Li, Yunling Yang · 2024
LDPC codes have been widely used to deal with noise interference and improve the reliability of the system due to their excellent error correction performance. At the same time, with the increase of storage density in digital storage devices, LDPC codes are also applied to the error check and correction (ECC) module in the storage device controller to solve the random flipping of stored data bits. In this paper, the PEG algorithm is used to construct a QC-LDPC code with high code rate in the ECC module, and the design simulation of the decoder based on the FPGA platform is carried out with reference to the layered minimum sum algorithm. Finally, the decoding results are analyzed under the condition that several bits of data are randomly flipped in the storage device. The decoder in this study can achieve a throughput of 8.49Mbps at a 50MHz clock.