Efficient RTL to GDS II Flow for Finite State Machine Integration: A Physical Design Approach
Amit Shohal, Jasbir Kaur · 2024
This paper describes a thorough process for using Cadence tools to partition, arrange, and route a circuit for a finite state machine. First, the Cadence NC Launch tool is used to simulate Verilog code to confirm the circuit’s operation. The Genus tool is then used to synthesize the RTL code into a gate-level netlist. For the gate-level netlist, measurements related to power, area, and timing are provided. Afterward, using a 90 nm library file, the produced netlist is used for placement and routing within the Cadence Innovus tool throughout the physical design phase. Power, area, and timing characteristics are monitored at several stages, such as pre-CTS, post-CTS, and post-routing. Notably, in the post-CTS phase, the overall power is reduced to 19.36 mW, with an area of 202.56 um2and timing of 9.31 ns, showcasing the efficacy of the proposed methodology. Additionally, a GDS II file is generated as part of the final output.