Procedural Design, Verification and Implementation Framework for Analog Amplifiers
Veeti Lahtinen, Santeri Porrasmaa, Marko Kosunen, Jussi Ryynänen · 2024
This paper presents a modular, parasitic-aware, process agnostic design and verification procedure. The procedure utilizes TheSyDeKick simulation and verification framework in combination with Berkeley Analog Generator (BAG). BAG is utilized to programmatically construct the schematic and layout in order to provide the parasitic component information for the algorithmic optimization procedure. This enables the most accurate definition of transistor sizing parameters to obtain the desired linearity, speed and noise performance. As the generation, extraction and design procedures are fully automated, this remarkably speeds up the design exploration. The presented procedural optimization is extensible to wide range of analog building blocks, and the effectiveness of method is demonstrated in context of a single-stage operational transconductance amplifier (OTA). The proposed method incorporates an algorithm that automatically sizes the design to achieve minimal current consumption for a given speed specification and provides a manufacturing-ready circuit implementation. The algorithm is demonstrated to effectively converge on final designs for various speed specifications with two distinct semiconductor processes.