XOR-Free Approach for Implementation of Polar Encoder
Navin Kumar, Deepak Kedia, Gaurav Purohit · IEEE Embedded Systems Letters · 2024
This letter presents a new algorithmic approach to construct an XOR-Free architecture for a nonsystematic polar encoder (NSPE). Optimization of XOR units is the main concern while implementing NSPE, which consumes a significant amount of dynamic power. To generate polar sequences of code length N, the approach uses$(N/2)-1$binary patterns extracted from the$(N/2)^{\mathrm { th}}$order generator matrix$G_{N/2}$instead of$G_{N}$. The algorithm reduces the logical operations by virtue of the recursive patterns, thereby improving hardware (HW) cost. The pattern logics are inferred with 2:1 multiplexers and inverters, making the implementation XOR-Free. An auto HDL code generation script is written targeting variable code lengths ($2{^{{3}}} \leq {N} \leq 2{^{{10}}}$) for direct comparison with similar approaches, viz. stage folded and punctured NSPE design. The results show that the proposed architecture improves area by 31%–83% and power consumption by 15%–57% for various N and code rates ($R{=}1$, 1/2) on Virtex-6 FPGA devices.