Approximate Multiplier for Optimized Power and Delay
Y. Harsha Vardhan, A Madhumitha, Dhanush P. Kumar, Kirti S. Pande, Sangeetha Kamatchi, Navin Kumar · 2023
Approximate multipliers which allow certain level of acceptable error becomes important in many applications such as computer Vision, digital signal processing (DSP), machine learning, and artificial intelligence. This work presents an implementation of an approximate multiplier using a modified Wallace tree design that combines full adders, half adders, and 42 approximate compressors. It uses the PolarFire silicon on chipt (SoC) Icicle Kit FPGA MPFS250_ES and Libero Soc simulation software. The resulting average error percentage is found to be $\mathbf{2 1 . 9 \%}$ along with the reduction in delay by $23.94 \%$.