Analyzing Area and Latency Overhead in C and RTL Locked Designs
Praveen Karmakar, Divyanshu Nauni, Chandan Karfa · 2023
Modern integrated circuit (IC) design hubs have adopted the fab-less design methodology for developing their System on Chips (SoCs). This allows for unreliable entities to operate at various IC supply chain nodes, posing security concerns such as IP piracy, counterfeiting, and overproduction of ICs. Logic locking is a widely accepted technique for securing modern IC designs against such threats. However, logic locking imposes additional resource constraints and introduces area and latency overhead in the original design, thereby affecting its efficiency and performance. This report analyses the area and latency overhead incurred when an original IC is locked at the behavioural level (C) and register transfer level (RTL). The design is locked to ensure uniform locking in both the C and RTL designs. Experimental results show that locking at RTL has less overhead than its equivalent locked C code.