A Lossless-Ethernet-Based Interconnect for FPGA Clusters Toward FTQC
Yoshito Higa, Yasunori Osana · 2024
FTQC (Fault-Tolerant Quantum Computing) requires quantum error correction processing, and our research group aims to realize quantum error correction using an FPGA cluster. The cluster requires a high-speed and low-latency interconnection network among FPGAs. RoCE (RDMA over Converged Ethernet), which prevents frame loss by appropriate flow control and achieves high performance and reliability, is becoming popular in data centers. Our research group aims to implement lossless Ethernet transport between FPGAs to realize a lossless and low-latency interconnection network for FPGA clusters. We observed and analyzed RDMA flow control between Linux hosts as the preliminary study, and we confirmed that flow control is performed using ECN (Explicit Congestion Notification) under congestion. This paper describes the prospects for implementing flow control in the send/receive module of UDP communication for Ultrascale+ FPGA, based on the results of this analysis.