Heloc-NoC: High-Efficiency and Low-Hop On-Chip Communication in 3D Network-on-Chips
Lizhong Wang, Haoyu Wang · 2024
3D Integrated Circuits (3DICs) expand the area and capabilities of chips by utilizing vertical space. As these circuits become more complex, there is an increasing demand for advanced and efficient vertical communication to enhance their performance. While Network-on-Chip (NoC) traditionally facilitates 2D communication architectures for System-onChip (SoC) interconnections, it is also being adapted for 3D SoCs to expand conventional 2D SoCs into additional layers. However, existing routing algorithms for 3D NoCs primarily concentrate on congestion avoidance, traffic distribution, and thermal management. We propose a novel 3D NoC architecture, accompanied by a suite of adaptive routing algorithms tailored for routers positioned at various spatial coordinates within a 3D NoC framework. Named Heloc-NoC, this architecture is designed to achieve heightened communication efficiency, fewer hops, and more evenly distributed traffic through the co-design of architecture and algorithms. A novel router, named the MediCom Router, has been proposed as the core communication unit in the Heloc-NoC, which is responsible for reducing the number of hops in long routing paths. Heloc-NoC has demonstrated a reduction in hops by up to $\mathbf{5 7. 1 \%}$ and latency by average $18 \%$; an enhancement in throughput by average $17.3 \%$ under the random traffic patterns, with an approximate hardware overhead increase of $8 \%$ (LUT) and $14.9 \%$ (FF) in a 3D Multi-Processor System-on-Chip (MPSoC) integrating lightweight RISC-V cores.