Enhancing VLSI Performance: An Innovative Approach to 3-Parallel Polyphase Odd-Length FIR Filtering with Kogge-Stone Adder and Booth Multiplier
S. V. S. Prasad, N. Shyam Sunder Sagar, M V N Nithya Pushkala, Siddartha Silveri, Baindla Harshitha, Sreeja Chenna · 2024
This paper proposes a novel technique towards enhancing VLSI performance as 3-Parallel Polyphase Odd-Length FIR Filtering. Here, the design primarily consists of Kogge-Stone Adder integrated with Booth Multiplier to increase the speed and efficiency of the Kogge-Stone Adder. Traditional FIR filtering has its limitations on power consumption and area optimization. To address the issues, we make use of the architectural features of Kogge-Stone Adder and the computational efficiency of Booth Multiplier by introducing the 3-Parallel Polyphase composition to overcome the issues by increasing the processing speed while maintaining low-power constraints and a small chip area, both of which are critical factors in today’s VLSI applications.