CTFE: A High-Efficient Heterogeneous Cryptographic CGRA for Diverse Security Applications
Vu Trung Duong Le, Hoai Luan Pham, Thi Hong Tran, Van Duy Tran, Vu Tuan Hai, Yasuhiko Nakashima · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2024
Nowadays, cryptographic computation across various security applications necessitates the development of hardware that is not only fast and power-efficient but also flexible enough to support a range of cryptographic algorithms. Unfortunately, existing computing platforms for cryptography struggle to balance high flexibility, high performance, and low power consumption. To address these issues, this article introduces the crypto-tailored flexible engine (CTFE), a next-generation coarse-grained reconfigurable array (CGRA) for cryptography. Concretely, the CTFE incorporates four innovative ideas to achieve high flexibility and performance with high hardware efficiency: 1) processing element array (PEA) with dual-buffer lanes and multiplexer optimization; 2) high flexibility Hyper-ALU; 3) heterogeneous PEA; and 4) bi-tiered pipeline coordination. Real-time evaluation results on Xilinx ZCU102 FPGA at the System-on-Chip (SoC) level demonstrate that the CTFE is 1.13–14.3 times better in throughput and 55.3–14 232 times better in energy efficiency than state-of-the-art CPUs. Experiments on an ASIC 45 nm CMOS technology show that the CTFE consumes the power of 1.06 W, occupies an area of$2.77 \; \text {mm}^{{2}}$, and operates at the frequency of 510 MHz. In comparison to existing CGRA solutions, CTFE outperforms 1.63–20.23 times in throughput and 1.61–73.2 times in area efficiency.