Formal Verification for Logical Circuit Design Optimization in Computer Architecture
Ashwini Kumar, Neeraj Sharma, Baishakhi Debnath · 2024
Formal verification is the process of proving a digital logic design’s accuracy by checking whether it mathematically follows specific requirements (or classical properties). Its basic philosophy is to precisely and strictly demonstrate that a design must meet its needs. The systematic construction of reliable and efficient computer architectures is paramount. When checking correctness and optimality, such methods as abstraction and symbolic model-checking, automatic theorem proving, and proof methods are adopted. Automatic techniques for handling large complex designs that require quick design generation, followed by manual methods, can be used to double-check the automatic ones. Still, testing and simulation are essential steps in the design process to locate errors hidden in the design that may not otherwise be apparent. In this fashion, one can design a logical circuit that satisfies specified performance standards before implementing it in natural systems.