Design & Implementation of Efficient Full Adder Cell Using Adiabatic & Reversible Logic
Rohan Bansal, Poorvika Singh, Nitin Sachdeva · 2024
Digital circuits with improved power efficiency and lightning-fast performance are becoming more and more necessary. Processors, which are essential for day-to-day activities, carry out a variety of intricate arithmetic and logical operations, frequently involving adders. To solve this, a full adder that minimizes heat dissipation into the surrounding environment is implemented using reversible logic and adiabatic logic, greatly reducing energy loss. As a result, circuits using this logic will operate quickly and efficiently. The suggested adiabatic full adder has a novel architecture, two output bits that indicate the sum and carry, and an adiabatic charging method. In adiabatic logic, the power consumption of the full adder is reduced by $51.88 \%, 48.54 \%$, and 49.68%, respectively, compared to the 16T Pass Transistor Logic (PTL) with Transmission Gate (TG) full adder, 14T PTL with TG full adder, and CMOS full adder. The suggested reversible full adder is based on reversible logic, the information is lossless as the input vector can be recovered from the output vector. The delay time is slashed out by $90.33 \%, 85.97 \%$ and 98.29% respectively when differentiated with 16T PTL with TG full adder, 14T Pass Transistor Logic (PTL) with Transmission Gate (TG) full adder and CMOS full adder.