Design and Synthesis of State Transition Graph Based Area Efficient Sequential Multiplier
Satyanarayan Padhy, Prabhat Kumar Patnaik, Abinash Rath, Sandipan Pine, Rajesh Kumar Misra · 2024
Combinational multipliers operate fast but require a significant amount of silicon area. As area is an important consideration, it can be reduced at the expense of performance by scheduling the sub-operations of the multiplier to execute in successive clock cycles. Sequential multipliers are compact, require fewer adders, and are amenable to pipelining. The area required by combinational multipliers grows geometrically with the word length. Still, the area of a sequential multiplier does not grow significantly with the word length, and the number of clock cycles required to complete a multiplication also grows in a linear manner rather than exponentially with the word length. The paper presents the design and synthesis of a sequential multiplier using a state transition graph (STG) controller. The proposed multiplier is designed and synthesized using Verilog programming in Xilinx ISE and the cadence tool. Simulation results and RTL diagrams are presented in comparison to different size multipliers and combinational Booth multipliers to validate that the area of the sequential multiplier does not increase exponentially with the multiplier’s size increase. FPGA implementation has been done to validate the operation of the proposed design