A Comparative Analysis of 8-Bit Parallel Prefix Adder Architectures
Manne Bharathi, Virupakshi Madhurima, Golla Sandhyakumari, M. Poornima, Saleha Tabassum · 2024
Digital adders are crucial parts of contemporary computer systems that influence the efficiency of specific arithmetic processes. Parallel prefix adders, like Sparse Kogge, Hancarlson and Brent Kung enhance performance by calculating results leading to faster and more efficient arithmetic operations compared to traditional adders that process data sequentially. This paper thoroughly compares four 8 bit designs; Sparse Kogge, Han Carlson, Brent Kung and Binary Coded Decimal (BCD) adder. Evaluation criteria include propagation latency (ns) power consumption (W) and area utilization (LUTS). When comparing the Brent Kung adder with the BCD adder there is a 18.33% increase in propagation delay but a significant 83.87% decrease in power consumption and a fifty percent reduction in area usage. The primary focus of the Hancarlson adder is power efficiency leading to an ${8 7. 1 0 \%}$ drop in power usage but a substantial 93.49% increase in propagation latency. The Sparse Kogge adder strikes a balance with a 58.06% decrease in power consumption and a moderate 18.75% reduction in area utilization while maintaining a propagation delay, as the BCD adder. These results illustrate trade-offs between various adder architectures in terms of power, latency, and area utilization. These designs are designed and simulated using Xilinx Vivado 2022.2 software.