HUNBN, a 1.77MB Digital In-Memory-Compute SoC for edge applications achieving 126 TOPs/W (4b) at macro level and 24 TOPs/W at SoC level.
Weijie Jiang, Cédric Caron, Prabhat Avasare, Marc Pauwels, Marian Verhelst, Wim Dehaene · 2024
This work introduces HUNBN, a fully Digital In-Memory-Compute (DIMC) System-on-Chip (SoC) using 16nm FinFET CMOS technology. It outlines three significant advancements: (1) A DIMC macro architecture that consolidates only the essential components—bit cell array, multiplier, and an initial stage adder tree—thereby minimizing design complexity and enhancing customization opportunities. The more intricate, yet less parallel, subsequent stage adder tree is synthesized. (2) The implementation of a standard foundry 6T bit cell for DIMC data storage, drastically increasing the memory density. (3) The adoption of synchronous operation for the DIMC macro, enabling wide range voltage-frequency scaling. These strategic innovations culminate in remarkable achievements: a macro-level efficiency of $126 \mathrm{TOPs} / \mathrm{W}$, an SoC-level efficiency of $24 \mathrm{TOPs} / \mathrm{W}$ for 4 -bit operations, coupled with a high memory density of $509 \mathrm{~KB} / \mathrm{mm}^{2}$ and a computing density of 1.27K MAC/mm². These metrics highlight the system’s energy efficiency and its capability to facilitate the inference of advanced CNN models directly on edge devices.