FPGA Implementation of Normal Basis Multiplier Using Reversible Logic
R. Pandimeena, S. Aathilakshmi, D. Mohamed Vaheen, Harinesh Vijay, K Mridhullashree, Blessy Sam. A. S · 2024
Reversible logic has emerged as a pivotal technology in recent years, playing a significant role in addressing critical concerns such as energy consumption reduction, power minimization, and advancements in quantum computing. It is also used to find faults in the circuit. In these circuits, designing of multipliers is an essential part of VLSI circuit implementation. Multipliers are critical for numerous arithmetic operations, including multiplication of binary numbers, which forms the backbone of various computational tasks. There is a greater number of existing works available, which is related to reversible logic. Although a substantial body of research exists in the field of reversible logic, there remains a persistent interest in pioneering innovative designs that push the boundaries of efficiency and functionality. This interest is driven by the ongoing demand for more streamlined, energy-conscious, and fault-tolerant circuit implementations. In the realm of reversible logic, various methodologies have been developed for the design of reversible multipliers. This study is centered on the creation of multiplication circuits and their diverse forms through the application of reversible logic. The research also involves a comprehensive analysis of several key reversible logic parameters, including the number of gates (NOG), garbage outputs (GO), constant inputs (CI), quantum cost (QC), delay (D), depth, and total cost (TC). Furthermore, a comparative assessment is conducted, contrasting the various multiplier types with prior research efforts. This examination underscores the advantages and disadvantages associated with each type of multiplier.