Feasible Implementation of ALU for Next Generation Processors
Radha. N, M. Maheswari, A. Backia Abinaya · 2024
This paper describes the VLSI implementation of an efficient 8-bit Arithmetic and Logical Unit (ALU). This ALU is an essential block in any central processing unit that drives the entire data processing. This paper introduces two feasible implementations of the 8-bit ALU: the ALU using parallel prefix adders and the clock-gated ALU using parallel prefix adders. In the first methodology, ALU implementation is done with parallel prefix adders such as the Kogge-Stone adder, the Brent-Kung adder, the Ladner-Fischer adder, and the Han-Carlson adder. The inclusion of these high-speed adders brings out the ALU as an energy-efficient design in terms of power consumption, area consumption, and propagation delay. To reduce the dynamic power consumption additionally, the second methodology uses the clock gating technique to implement an 8-bit ALU using parallel prefix adders. The clock-gated 8-bit ALU implementation using parallel prefix adders extensively reduces power consumption without sacrificing speed. However, it increases the area occupied due to extra hardware logic. Yet, the trade-off is compensated with the help of parallel prefix adders. Simulation results using Cadence 90 nm technology reveal that the power consumption, area consumption, and propagation delay of the 8-bit clock-gated ALU using the Han-Carlson adder decreased by 19.92%, 8.25%, and 31.77%, respectively. To make the proposed ALU implementation suitable for next-generation processors, 16-bit ALU and 32-bit ALU are also implemented using Cadence 90 nm technology.