Systolic Array Architecture for Multitasking Neural Processing Unit
Peidong Lin, Hu Zhang, Lin Li, Yun Li · 2024
Google’s Tensor Processing Unit (TPU) verifies the power of the systolic array architecture in accelerating specific computational tasks. Since the present Neural Processing Unit (NPU) design faces challenges in multitasking, this paper proposes a multitasking NPU architecture based on the systolic architecture. Performance improvement and latency optimization are achieved by using modules for an efficient scheduler and a mobile adder. The resultant NPU architecture facilitates parallel computation and task prioritization. Further to a random forest method to simulate hardware resource consumption, a genetic algorithms is used to achieve multi-task weight optimization, allocating resources to minimize consumption. Simulation results show a 26.2% improvement on processing element utilization, and a reduction on hardware logic resources by 5.1%, memory usage by 48.46% and simulation time by 60.38%.