A Rapid Analysis Method for VME Bus Transaction Function in Open-Source IP Cores Based on Signal Transition Graph Model
Xiangfen Wang, Xilong Wang, Jinyong Yao, Runjia Xing · 2023
The adoption of open-source IP cores in System on Chip (SoC) design requires more effort in analyzing, understanding, and evaluating function verification, which is less convenient than proprietary closed-source IP cores due to the increasing complexity of IP core structures. This study proposes a signal transition graph (STG)-based function verification method for VersaModule Eurocard (VME) bus transactions of an open-source peripheral component interconnect express (PCIe) - VME bridge IP core to reduce verification time. First, the behavior of VME bus transactions defined in the VME64x standard specification is mapped to a reference STG model. Next, the implementation of bus transactions in the open-source IP core code is mapped to a code implementation STG model. Subsequently, a comparative analysis is conducted between the code implementation STG and the reference STG. Finally, an assessment is made to determine the function compliance of the open-source IP core with the VME64x standard in terms of implementing VME bus functions. The results show that the key read transaction transfer and write transaction transfer function implementations of the VME side in the IP core are essentially consistent with the requirements specified in the standard using the proposed function equivalence checking method. This demonstrates the applicability of the proposed methodology for swiftly verifying the correctness of VME transaction function implementation.