Coverage-Driven and Constrained-Randomized Sub-System Level Verification Methodology for RISC-V Based SoCs
Muhammad Kashif Minhas, Haroon Waris, Yasir Farooq, Nasir Mohyuddin, Sajid Baloch · 2023
This paper presents the robust sub-system level verification framework for RISC- V based SoCs. The sub-system level verification ensures that the individual modules of a system under test are functioning correctly. The proposed framework adopts a hybrid model verification environment based on coverage driven verification (CDV) and constrained randomized verification (CRV) methodologies. Moreover, the universal verification methodology (UVM) is adopted to make testbench reusable and configurable. The SweRVolf, a RISC- V-based SoC with a dual-issue 9-stage SweRV-EH1 core, is used to prove the applicability of proposed sub-system verification environment. The sub-system design under verification (DUV) consists of AXI-to-WB bridge, Wishbone interconnect and GPIO interface. The proposed framework verifies each module first at IP level and then integrates all the universal verification components (UVCs) together to perform sub-system level verification. The CDV is used for coverage closure and covering all possible corner cases while the CRV is considered for exhaustive and complete verification of the D UV. 25 different random and directed tests have been applied to the sub-system DUV. For functional coverage 21 separate cover-groups are written. Each cover and cross cover-group targets specific feature of the DUV. The proposed hybrid verification model is able to achieve 100% toggle coverage both at IP and sub-system level. The proposed approach is best suited for applications focusing sub-system level designs using pre-verified IPs. The proposed verification framework could seamlessly be integrated with any RISC- V based SoCs testbench environment assuming that the same sub-system design topology is considered.