Time-Triggered Inference on FPGAs
Yosab Bebawy, Michael-Christian Schmidt, Hamidreza Ahmadian, Aniebiet Micheal Ezekiel, Roman Obermaisser · 2024
Safety-critical AI systems demand the utmost reliability to prevent catastrophic outcomes. However, conventional AI hardware accelerators, such as the Versatile Tensor Accelerator (VTA), suffer from limitations in predictability and reliability due to inherent variability in event-driven task execution and the lack of precise timing control. These limitations make them unsuitable for safety-critical applications where erroneous or untimely operations could lead to catastrophic consequences. This paper proposes a novel time-triggered VTA (TT-VTA) architecture specifically designed to address the shortcomings of conventional VTAs and enhance safety and reliability in safety-critical AI systems. The TT-VTA architecture utilizes pattern-based timing schedules which are generated by a software simulator that integrates DRAMSim2 to simulate memory-related instructions as well as by a cycle-accurate simulator to provide accurate cycle counts for non-memory-related instructions. A comparative evaluation using a ResNet18 classification model demonstrates that the TT-VTA achieves identical classification accuracy while maintaining deterministic resource utilization and enabling precise timing control. Our proposed TT-VTA architecture demonstrates significant promise for enhancing the safety and reliability of AI systems in safety-critical applications.