Hardware Implementation and FPGA Prototyping of an Expectation Propagation-Based Receiver
Ian Fischer Schilling, Serdar Şahin, Camille Leroux, Antonio Maria Cipriano, Christophe Jégo · 2024
This paper presents a hardware implementation and FPGA prototyping of a flexible pipelined Expectation Propagation (EP)-based receiver that can handle QPSK, 8-PSK and 16-QAM constellations. The receiver implements a Frequency Domain (FD) Self-Iterated Linear Equalizer (SILE) based on EP to approximate the true posterior distribution of the transmitted symbols by a simpler distribution. Analytical approximations for the EP feedback generation process and the three constellations are applied to reduce the hardware complexity of the soft mapper/demapper architectures. The implementation results show a significant reduction in clock cycles due to the pipeline and an efficient usage of FPGA resources, underscoring the effectiveness of the proposed architecture.