A Machine Learning-Based Approach for Performance Prediction and Optimization of Network-on-Chip Designs
Jiapeng Zhu, Leran Wang, Haoran Teng, Wenxin Xu, Guozhu Liu · 2024
This paper introduces a machine learning-based approach for optimising network-on-chip (NoC) designs. Utilising a Multi-Layer Perceptron (MLP) model and extensive simulation data, it accurately predicts NoC latency, power consumption, and area. The study validates the efficiency of the MLP model with prediction accuracy exceeding 98%. Furthermore, leveraging the optimised model, a novel design optimisation strategy is proposed to minimise latency under specified area and power constraints. Verification of the optimized design was conducted through the implementation of the Verilog HDL and subsequent hardware validation. This study indicates that, while maintaining constant latency, area optimization reaches 96.2% of the baseline model, and power consumption optimization reaches 99.1%. These papers provide a dependable data-driven methodology for future network-on-chip designs, enhancing design efficiency and performance.