A Dynamic Window Size-Based VLSI Architecture Design of Moving Average Filter and Its Vulnerability to Hardware Trojans
Moitreya Chaudhury, Binit Kumar Pandit, Ayan Banerjee · 2024
This paper investigates the vulnerability of VLSI architecture to hardware trojans, with a specific focus on moving average filter-based digital signal processing (DSP) systems. A highly parameterized and scalable window-size moving average filter is designed. A novel hardware trojan architecture is proposed and injected into the design with minimal area overhead on Xilinx’s Zynq UltraScale+ MPSoC FPGA board. The malicious circuit will make the desired output noisy, decreasing the signal-to-noise ratio and thus hampering the circuit’s overall functionality at the register transfer level (RTL).