Generic methodolgy and solution for Additive Jitter correction in Mesh based clock architectures
Sri Sakthi Santhanam, Ankita Dhole, Sudheer Anumala · 2024
Additive Jitter is a critical parameter of the clock buffer in the system clock design. Mesh architectures and clock buffers are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations between signal nodes spatially distributed over the chip. In a clock mesh, the multi-driver structure is used to distribute clock signals to various parts of chip efficiently. However, they can introduce various timing problems that result in GLS (Gate-Level Simulation) failures. This paper demonstrates solutions to the problem of additive jitter caused due to mesh-based complex clock architectures in ATPG timing simulations. This methodology helps in saving debug time and huge simulation run time while awaiting the clean SDF (Standard Delay Format) from physical design team for any complex designs and is verified by test results.