Automated Design and Configuration of RISC-V based NoC-MPSoC Framework on FPGA
Mekala Bindu Bhargavi, Sai Siddharth Rokkam, Sri Parameswaran, J. Soumya · 2024
The increasing complexity of System-on-Chip (SoC) architectures requires efficient data transfer and integration of multiple processing units. Network-on-Chip (NoC) technology is essential for managing communication within Multi-Processor Systems-on-Chip (MPSoCs). Manual design of NoC frameworks is time-consuming, error-prone, and costly. This paper presents an automated framework for generating and configuring RISC-V based NoC-MPSoC topologies on FPGAs. By automating the creation of MxN mesh-based topologies (M is number of rows and N is number of columns), including routers, network interfaces (NIs), and processors, the proposed framework reduces manual intervention, accelerates the design process, and minimizes human errors. The framework’s adaptability and scalability are validated across various router sizes, confirming its effectiveness in optimizing resource usage and reducing costs. The automated design was implemented and verified using AMD Vivado, Integrated Logic Analyzer (ILA), and Virtual Input-Output (VIO) tools on a ZedBoard.