Compiler for Hardware Design of Convolutional Neural Networks with Supervised Learning Based on Neuromorphic Electronic Blocks
Mikhail O. Petrov, Eugene A. Ryndin, N. V. Andreeva · 2024
Deep neural networks are a powerful tool for solving a variety of problems, but software implementations have a number of drawbacks related to power, runtime and energy consumption. Hardware implementations can help overcome these limitations. In this paper, we present a compiler for convolutional neural networks with supervised learning, which allows to create functional circuits of ResNet architecture networks using five general-purpose neuromorhic electronic blocks. The proposed approach makes it possible to design general neural networks based on reconfigurable blocks. The functional circuit implies disabling the part of the circuit responsible for the learning mode, which allows training different networks using a single functional block.