An Optimized Voltage Scaling Circuit for Increasing the Linearity and Input Voltage Range of Voltage to Time Converter Circuits
Bo-wei Shih, Jia-Yi Lee, Ying Chen, Woei‐Luen Chen · 2024
Voltage-to-time converters (VTCs) employing delay lines demonstrate nonlinearity in the correlation between input voltage and output time. Although selecting a more linear segment helps alleviate nonlinearity, it diminishes the usable input voltage range of the VTC. Furthermore, chip process variations lead to output time drift in the VTC, posing challenges in accurately quantifying input voltage. A voltage scaling circuit, composed of voltage followers, is employed as the input stage of delay lines to provide a bias and voltage gain for reshaping the input voltage of the VTC. This approach not only improves the linearity of the VTC but also extends the input voltage range to achieve nearly rail-to-rail swing. A comparative analysis based on the simulation results, conducted using the UMC 0.18um process, demonstrates the effectiveness of the proposed approach.