PireSPM: Efficient and Recoverable Secure Persistent Memory for Multi-cores
Weijie Huang, Bohong Zhu, Jiwu Shu, Shu Li, Zhengyong Wang, Yu Gao · 2024
Secure persistent memory (PM) systems have to guarantee the crash consistency for secure data, which requires atomically persisting both data and its security metadata (e.g., the counter and Merkle tree nodes). Existing work introduces persistent registers and uses the redo-style method to ensure the atomic durability of the data and security metadata for a single-core system. Unfortunately, their performance decreases sharply in multi-core secure PM systems because the atomic durability guarantee procedure for each write request is serialized.In this work, we propose PireSPM, a pipeline-based and recoverable scheme for secure persistent memory for multi-core architecture. PireSPM supports processing multiple atomic durability requests at a time without incurring recoverability problems to the secure PM. We further optimize PireSPM by combining Merkle tree updates and reducing the latency incurred by the atomic durability guarantee without breaking the system’s recoverability. Experimental results show that PireSPM with all these optimizations achieve up to 1.49× speedup and 4.97× speedup respectively over the state-of-the-art method in 1-core and 16-core systems.