Run-time Reconfiguration of NoC in Xilinx ACAP Architecture
Aman Gupta, Sagheer Ahmed, Abhishek Kumar Jain, Ygal Arbel, Abbas Morshed, David Schultz · 2020
The Xilinx 7nm Versal product family features a new architecture known as Adaptive Compute Acceleration Platform (ACAP) which brings heterogeneous compute, IO resources and programmable logic (PL) together in a software programmable platform. Versal Network-on-Chip (NoC) ties all the device elements together with a single, global and high-speed switching network that supports multiple Tbps of data movement. Usually, any standard hardware NoC system implements use-case specific routing to provide predictable latencies and dedicated performance for certain traffic types. Dynamic routing can provide intelligent adaption to faulty links and traffic patterns. However, implementation of dynamic routing in a hardened NoC system is not trivial. The hardened NoC in the Versal product family implements use-case specific routing and allows NoC routes to be updated at run-time. This paper shows how this architecture is implemented and the benefits that various applications can avail from it.