Efficient 1-Bit Full Adder Implementation with Reduced MOSFET Count
D. R. Premachand, K M Srikantha · 2024
The main objective of proposed work apply the minimal number of MOSFETs and non-complementary inputs are used. The proposed work presents a comparative study of two types of 1-bit full adder (FA) circuit architectures. First full adder architecture circuit design uses Two XOR gates with 3 transistors and one 2:1 Multiplexer with Two transistors, second full adder architecture circuit design uses Two XNOR gate with 3 transistors and one 2:1 Multiplexer with Two transistors are discussed. These two architectures reduces complexity of the design and counts lower number of transistors compared to the existing FA circuit. The design is implemented on 180 nm CMOS technology with 1.8 V supply. Simulations are performed by using LTSpice and the performance is evaluated in terms of power consumption, propagation delay and Power Delay Product (PDP) for both the architectures. The results indicate that, the proposed FA with RMC deliver the best performance among all FAs.