Design and Optimization of Configurable L1D Cache for High Performance R-DSPs
Jinyu Li, Jianghua Wan · 2024
This paper focuses on the high-performance and low-power design of the L1D Cache for DSP applications. It presents the overall architecture of the level-1 data cache, utilizing a dynamic cache optimization strategy. During runtime, relevant registers are configured to adaptively adjust the cache size. A dynamic bandwidth management design for multiple requests is proposed, optimizing the memory hierarchy, data transfer paths, and communication with external devices to maximize system performance and enhance fairness. Simulation results indicate that with the dynamic bandwidth management architecture, the average blocking time for the lowest priority requests is reduced by approximately 17.32%.