FPGA Implementation of 2D Convolution using Diverse Adder – Multiplier combination
Shwetha Bhavikatti, Aswini N · 2024
This research study gives a comparative analysis of two distinct multiplier-adder combination, a Vedic multiplier with Ripple carry adder (VMRCA) and a Wallace tree multiplier with Kogge stone adder (WMKSA), applied in the context of 2-dimensional convolution operation. The proposed work aims to assess the performance metrics such as the number of LUTs (Look Up Tables), Power, and Delay associated with each architecture. The Vedic Multiplier, rooted in ancient Indian Mathematics, and the Wallace Tree Multiplier, which offers parallel processing for improved efficiency are utilized here. Through comprehensive evaluation and experimentation, this paper provides insights into the trade-offs between these architectures, providing valuable inputs for their usage in the field of High-performance computing applications, Image Processing, and Convolution operations. The entire software simulation is performed on Xilinx ISE and prototyped on Xilinx Spartan 6 FPGA board.