Discrepancy in Execution Time: Static vs. Dynamic Reconfigurable Hardware
Darshika G. Perera, Kin F. Li · 2024
Utilization of FPGAs has increased dramatically in various application domains, mainly due to their unique traits. Especially, FPGAs' dynamic partial reconfiguration feature enables multiple and complex/large applications to be executed on a single chip, regardless of them fitting on chip. From our previous work on dynamic partial reconfigurable hardware for complex applications, we observed a discrepancy in execution time between static reconfigurable hardware (SRH) versus dynamic reconfigurable hardware (DRH). In this paper, we perform additional experiments/analysis to investigate this discrepancy, using a simple adder and a multiplier to compose our SRH and DRH designs. Our experimental results and analysis demonstrate that this discrepancy is not due to actual add/multiply operations, but due to difference in read/write operations to/from SDRAM for SRH vs. DRH, and difference between the two hardware versions.