A Configurable AES Implementation on FPGA for Secure 5G Systems
Prashamol Prakashan, Harsh Gupta, S. Nalesh, Kala SI · 2024
Advancement in technology and computational power has paved path for data security challenges in 5G communication. Confidentiality and integrity of data plays a key role in 5G networks. 5G systems are employed with different security protocols to facilitate security in high speed wireless communication. Among the various security systems available, Advanced Encryption Standard (AES) is observed to have better throughput and hardware efficiency. AES is one of the popular cryptography algorithms with three variants namely, AES-128, AES-192 and AES-256, each of which offers different levels of security. In this paper we present a configurable architecture for implementing the three variants of AES on hardware, so that the security level can be changed depending on the application. The proposed architecture has been implemented on Xilinx Virtex Ultrascale FPGA with an operating frequency of 175 MHz. The implementation results have been analyzed in terms of latency and hardware utilization.