Design and Implementation of Fundamental Calculation Method by using the CORDIC Algorithm
Karthik. A, Reddy R. Ramana, Ramkumar. K, Santhosh. R, Robin. K · 2024
The primary design factors of VLSI circuits are area, power, and analysis of the large-scale integration. The multiplier is a crucial component in the design of DSP systems, graphical systems, multimedia systems, and microchips. Methods: Implementing a low-complexity digital multiplier using the CORDIC algorithm, a well-known interactive algorithm for performing rotations in Verilog design. The primary objective of CORDIC is to increase the clock speed and reduce the critical path delay. A power- and area-efficient high-speed bit multiplier model based on Fast Fourier Transform (FFT) multiplication is proposed for CORDIC processes. Concluding: The shift-accumulator comprises several highly regular and adaptable bit-slices and only contains three blocks: latches, exclusive OR gates, and multiplexers. A differential binary bits timed logic approach, suitable for high-speed and low-power operation, is used for the multiplication. The result is reduced delay, power consumption, and complexity.