From Bugs to Fixes: HDL Bug Identification and Patching using LLMs and RAG
Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler · 2024
In this paper, for the first time, we present a methodology that combines Retrieval Augmented Generation (RAG) with Large Language Models (LLM) to help with the identification and patching of Verilog Hardware Descriptive Language (HDL). If the methodology fails to patch a bug, an iterative and systematic bug patching closure technique is used. Additionally, we classify different types of bugs that are found in hardware and assess the performance of our approach for identifying and patching of bugs from each category. We tested our approach on three different OpenTitan designs and found out that our methodology can patch all bugs as long as they are not constant values.