Dora: A Low-Latency Partial Reconfiguration Controller for Reconfigurable System
G.Q. Zhang, Lisong Shao, Hanqian Wu, Xiaotian Gu, Xinyi Zhang · IEEE Transactions on Circuits & Systems II Express Briefs · 2024
Dora, a low-latency Field-programmable gate array (FPGA) partial reconfiguration (PR) controller, is proposed in this brief to address the latency challenge encountered by traditional solutions in highly real-time reconfigurable systems. First, based on the constructed refined cost model, key factors for minimizing latency in Host-to-FPGA reconfiguration process are analyzed. Subsequently, utilizing the established producer-consumer model, the reconfiguration mechanism (scatter gather-streaming-based hybrid transmission) and training method (adaptive overclocking of the Internal Configuration Access Port, ICAP) in Dora aim to enhance production of configuration bitstream while achieving efficient consumption. Ultimately, experiments demonstrate that Dora outperforms existing solutions in pivotal aspects: (i) It slashes FPGA resource utilization by over 60% while attaining a reconfiguration rate close to the theoretical peak of 99.6%, (ii) it reduces latency to just 11.1 ms, representing only 2.6% of the latency of the standard Xilinx solution, (iii) additionally, its open-source nature fosters broader adoption and utilization among the research community.