HELP: Highly Efficient and Low-Latency Hardware Accelerator for Integer Polynomial Multiplication
Pengzhou He, Tianyou Bao, Çetin Kaya Koç, Jiafeng Xie · 2024
Integer polynomial multiplication has been frequently used in post-quantum cryptography (PQC) schemes. In particular, unequal-sized integer polynomial multiplication, i.e., the coefficients from two input polynomials are not the same, has recently drawn significant attention from research communities. Besides that, this polynomial multiplication often involves specific parameter setups, such as power-of-two poly-nomial degree and modulus, efficient acceleration of this type of polynomial multiplication thus becomes an interesting topic, especially on the hardware platform. This paper follows this trend to develop a Highly Efficient and Low-latency Polynomial multiplication (HELP) accelerator for the targeted integer poly-nomial multiplication. First of all, We presented a new algorithm for the targeted polynomial multiplication for high-performance operations. Then, we proposed the HELP accelerator, giving its detailed architectural description. Finally, implementation results and comparisons are provided to demonstrate the efficiency of the proposed accelerator. For instance, the HELP accelerator is found to have at least 36.99% equivalent area-delay product (eADP) than the reported implementations ($n= 1,024$). The outcome of this work can be extended further for related cryptographic accelerator desian and development.