MOHSKM: Meta-Heuristic Optimization Driven Hardware-Efficient Heterogeneous-Split Karatsuba Multipliers for Large-Bit Operations
Saketh Gajawada, Dantu Nandini Devi, Madhav Rao · 2024
The large operand sized multiplier is a pre-requisite for designing hardware crypto-accelerators towards achieving secure data transactions from the system-on-chip (SoC). Scaling up normal multipliers leads to latency issues, while Karatsuba multiplication aids, it is only explored in homogeneous operand splitting. There exists an entire design space exploration for non-homogeneous splitting to enhance the hardware traits. This work introduces a novel optimization enabled framework for generating hardware-efficient heterogeneous split karatsuba based multipliers for multiplication of large bit-widths. The framework is powered with Particle-Swarm-Optimization (PSO) method that evolves to the most optimal split of operands while utilizing compressors in the reduction tree architecture. The framework was investigated to generate heterogeneous-split Karatsuba multipliers for operands of size ranging from 16-bit to 256-bits. The heterogeneous split exhibits a 3% delay improvement in delay for 32-bit and 64-bit multipliers, a 8% power saving for 64-bit multiplier and shows a superior ADP gain across multipliers of different bit-widths investigated, exhibiting 11% improvement, 5.7%, and 11% for 256-bit, 128-bit, and 53-bit multiplier designs respectively. Multiplier design framework and files freely available for researchers and designers community.