SHIFFT: A Scalable Hybrid In-Memory Computing FFT Accelerator
Pragnya Sudershan Nalla, Zhenyu Wang, Sapan Agarwal, T. Patrick Xiao, Christopher H. Bennett, Matthew J. Marinella, Jae-sun Seo, Yu Kevin Cao · 2024
Traditional CMOS FFT accelerators face challenges in achieving faster and more energy-efficient computing because of the latency associated with butterfly adders and data movement between the processing element and DRAM. Additionally, it's crucial for these FFT accelerators to be adaptable to different FFT sizes. In addressing these challenges, we introduce a scalable hybrid in-memory computing FFT accelerator (SHIFFT), a hybrid architecture that combines RRAM-based in-memory computing with CMOS butterfly adders, achieving both low Energy Delay Product (EDP) and high scalability. We explore the design space to identify the optimal configuration of ADC precision, RRAM precision and crossbar size, taking into account other influencing factors. In our 45nm simulations, our hybrid IMC architecture, in its optimal configuration, demonstrates a$5.52\times$reduction in EDP and$43.32\times$improvement in FFT throughput compared to the state-of-the-art for an FFT size of 1024. Finally, this work sets up the framework to evaluate how the accuracy of FFT, on a speech dataset is affected by inherent quantization and variations in IMC designs.