A Method of Extracting and Visualizing Hierarchical Structure of Hardware Logic Based on Tree-Structure For FPGA-Based Prototyping
Junbo Tie, Guoteng Pan, Lin Deng, Changqing Xun, Li Luo, Li Zhou · 2024
FPGA-based prototyping is a valuable tool for verifying chips, and logic partition is a critical step involving using a hierarchical hardware structure as inputs. This paper proposes an effective method for extracting the hierarchical structure of hardware logic design. The process involves designing the RTMI and tree node data structure and developing an extraction algorithm based on the defined tree node. With this method, the synthesis information of each hardware logic module can be accessed only once to establish the hierarchical structure of the logic design. A method to visualize the hierarchy based on the tree structure is also proposed. To verify the effectiveness of the proposed method, an open-source RISC-V processor RTL code was used as the object of hierarchical structure extraction. The synthesis tool used is Yosys, and the visualization hierarchical structure is implemented within the open-source graphic library Graphviz. The experiment results demonstrate that the hierarchical structure of the processor can be accurately extracted and graphically shown.