Increasing the Efficiency of Hierarchical Fault Simulation through Functional Fault Clustering
Nikhil Sagar Modala, Lakshmanan Balasubramanian, Rubin Parekhji, Sule Ozev · 2024
Due to increasing defect rates and increasing complexity of mixed-signal circuits, evaluation of fault coverage for a given input, also known as fault simulation, has become essential. Established fault models in the analog domain are based on detailed transistor-level netlists. Existing fault simulation tools inject and analyze fault responses at this level of detail. However, extending fault simulation to large circuits, especially when digital signals and/or frequency translation is involved, can be difficult due to the nature of simulations. Designers work with models at higher abstraction levels where simulations are more efficient. Hierarchical fault simulation intends to bridge the gap between transistor-level fault simulations and the evaluation of fault manifestation at the system level. Hierarchical fault simulation aims to capture fault response behavior at the sub-block level and propagate this response to the system level using high-level models. In this way, the efficiency of fault simulations can be increased considerably without sacrificing the accuracy. In this paper, we aim to increase the fault simulation efficiency further by dropping some faults to be simulated through functional equivalency at the sub-block level. We use a fault clustering approach that is based on the fault response model parameters and simulate only a representative fault model for each cluster. The method is applied to a comparator model that is used in a flash Analog-to-Digital Converter (ADC) design. Experimental results show that the hierarchical fault simulation time can be reduced by a factor of 8–10 without sacrificing the fault simulation accuracy.