Watermarking Three-Dimensional NOC Architecture to Detect Malicious Intellectual Property
T. R. Dinesh Kumar, S. Sivasaravana Babu, M. Sheriff, A.N. Naveen, R. Pranavesh, A. Shiva · 2024
This study offers a novel 3D representation for network-on-chip (NOC) routering in contrast to traditional 2D models. The goal is to increase data transfer acceleration, productivity, reliability, and cost- effectiveness, particularly by lessening the impact of Trojan-infected files. By utilizing a three-dimensional routing architecture, the suggested NOC design enhances communication channels and interconnection, lowering latency and increasing data transfer speeds. The 3D NOC router exhibits enhanced resilience against Trojan attacks by integrating fault- tolerant techniques and innovative routing algorithms, all while preserving reduced power use and area overhead. Building system-on-chips with intellectual property from third parties has become a global trend, raising serious concerns about security vulnerabilities. In this work, we suggest a low-tech alternative defense strategy based on digital watermarking. Realistic SOC models and experiments in a range of applications demonstrate that our solution can considerably. Based on analytical results, the designed routing algorithm reduces total pin count by 58%, total logic element count by 2%, total memory bit count by 1%, reduces latency by 15%, reduces power consumption by 13.5%, and reduces area overhead by 65%.Hence this works is applicable in data security in wireless communication and wireless sensor network.