Power Side-Channel Verification in Hardware Designs
Khitam M. Alatoun, Ranga R. Vemuri · 2024
The security of hardware designs is seriously threatened by power side-channel attacks, wherein the adversary can expose confidential information by analyzing the power consumption in the design. This paper introduces a methodology for formal verification of the power side-channel leakage. Our model analyzes gate-level side-channel dynamic power and uses JasperGold for formal verification. Multiple System Verilog Assertions (SVA) are devised to capture various properties relevant to the power-side channel analysis. The verification process is executed on four distinct hardware designs. The outcomes demonstrate the efficacy of our approach in accurately detecting power-side channels in hardware. Additionally, an analysis of SVA failures enables the quantification of the leaked power.