Stage Delay Calculation Method Considering Effective Capacitance
Peiwen Zha, Jingjing Guo, Shugang Zhang · 2024
A key part of a static timing tool is its delay calculation engine-responsible for computing delay, slew, and waveform information from models of logic gates and interconnect parasitic. A stage delay calculator includes cell delay and wire delay. In previous studies, they are often independent. With the advancement of technology, the Miller effect and highly resistive load interconnect have increased the interdependency between cell and wire delay calculations. In this paper, we propose a stage delay calculation approach that utilizes effective capacitance(Ceff) to address the computation of delays and waveforms for both cells and wires. Furthermore, machine learning is employed in the calculation of wire delay, modeling the interconnects using Ceffs as a feature. Experimental results demonstrate that the proposed delay calculation method achieves an accuracy within 1.66% of the delays calculated by SPICE.