A 98.5 dB-SNR 0.14 mm2 Chopped Delta-Sigma Modulator with 1.2 μV Offset for Current Sensing Applications
Tianqiang Lin, Liwen Liu, Xiaochao Li · 2024
This paper presents a low-offset high-precision Delta-Sigma modulator (DSM) for current sensing applications. Due to amplifier offset voltage, the chopped switched-capacitor (SC) integrator exhibits dc voltage error during integration when the chopping frequency is lower than the modulator’s sampling frequency. A modified chopper timing control on the integrator is adopted to address this issue when the ratio of chopping frequency to sampling frequency is much lower, such as $1 / 12$. Additionally, system-level chopping (CHL) is designed in the modulator to mitigate the modulator’s offset. The post-layout simulation results show that the DSM achieves a peak signal-to-noise ratio (SNR) of 98.5 dB over $128-\mathrm{Hz}$ bandwidth at room temperature. MonteCarlo simulations show that it achieves an offset voltage of less than $1.2 \mu \mathrm{V}$. The modulator is implemented in $0.18-\mu \mathrm{m}$ BCD process, occupies $0.14 \mathrm{~mm}^{2}$, and draws $35 \mu \mathrm{A}$ from a $1.8-\mathrm{V}$ supply.