Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator
Alan P. Smith, Gabriel H. Loh, Samuel Naffziger, John Wuu, Nathan Kalyanasundharam, Eric A. Chapman, Raja Swaminathan, Tyrone Huang, Wonjun Jung, Alexander Kaganov, Hugh C. McIntyre, Ramon Mangaser · IEEE Micro · 2024
The semiconductor industry has deployed chiplet-based system-on-chip architectures for several years. Central to a successful chiplet-based product is the die-to-die interconnect technology between the chiplets. Based on product requirements, some chiplet designs can utilize a single interconnect technology such as 2-D signals over an organic substrate or higher-density 2.5-D integration technologies. With increasing demands on compute and memory capabilities, high-performance products are now moving to heterogeneous integration, which combines multiple advanced packaging technologies all within a single system on chip. To address the market demands for high-performance artificial intelligence solutions, AMD has introduced the AMD Instinct MI300X accelerator. This article details the chiplet interconnect design required to support a sophisticated package that takes high-volume heterogeneous integration to a new level.